As is well known, arrays of static random access memory (SRAM) cells can be used to maintain logic states corresponding to associated data values. Individual SRAM cells may be implemented, for example, using cross-coupled logic gates. It is desirable for SRAM cells to hold their stored logic states despite possible changes in voltage, temperature, or other operating conditions. It is also desirable for SRAM cells to permit changes in their logic states in response to write operations.
Unfortunately, existing SRAM cell designs often fail to provide high degrees of both stability and writeability. For example, as operating voltages of SRAM cells are reduced, their writeability can suffer. In particular, it may be difficult for write drivers and their associated SRAM cell access transistors to pull down nodes of SRAM cells in order to satisfactorily write logic low values into the SRAM cells, while working against pull up devices of the SRAM cells. As operating voltages of the SRAM cells approach the threshold voltages of the access transistors, this write problem worsens due to gate overdrive of the access transistors. Such overdrive conditions may occur, for example, when the power provided to the access transistor gates (e.g., from word lines of a memory device) exceeds that of the power supply of the SRAM cell.
In the well known six transistor design for an SRAM cell, write operations are accomplished by discharging a precharged bitline. Writeability is generally limited by the ratio of PMOS load transistors and NMOS access transistors of the SRAM cells. In order to perform satisfactory write operations, this ratio should be selected to permit nodes of the SRAM cells to be pulled down below a trip voltage of the SRAM cells. However, at lower temperatures, the threshold voltages of the NMOS access transistors can increase which may prevent them from turning on during such conditions, resulting in write failures.
Additionally, as SRAM cell operating voltages are reduced, readability can suffer. In this case, the internal nodes of the SRAM cells may be subject to read disturbance. For example, during read operations, the internal SRAM nodes may be inadvertently charged through the access transistors above a trip voltage of the SRAM cell, thereby causing the SRAM cell to switch logic states.
In order to minimize read disturbance and improve the static noise margin (SNM), it is generally preferable to reduce the size of NMOS access transistors. However, for writeability, it is generally desirable to increase the size of such access transistors. These competing design considerations can result in SRAM cells that suffer in readability or writeability, especially in low voltage designs.